Dual-Redundant Flight Control Computer

The dual-redundant flight control computer is the centralized computing unit of the flight control system, responsible for signal acquisition, interface processing, control/guidance law calculation, redundancy management, bit-in-time (BIT), and flight mode management. It adopts an architecture centered on the LVDS serial backplane bus, with dual-redundant configuration of the CPU, interface, and power module. It operates in a primary/backup mode, possessing fault tolerance capabilities and enabling operation even in the event of a single failure. The core processor uses the latest self-monitoring processor, improving the computational reliability of the processing module. It can be used in the flight control and management systems of medium to large-sized unmanned aerial vehicles (UAVs).